Apparatus for use in depositing articles in a receptacle and a sequence controller utilized therein

ABSTRACT

Apparatus is described for use in depositing bank deposit envelopes in a receptacle according to an enforced sequence of actions in a deposit cycle, each action having to take place within specified time periods. The apparatus includes error testing means terminating the deposit cycle at any stage thereof in which an action occurs deviating from the predetermined sequence or not within a time period specified in the sequence. The sequence controller includes a shift register having an output for each stage in the cycle, a logical gate for each stage which gate is enabled by a signal from the shift-register output of the preceding stage, and clocking means responsive to the output signals from the logical gates for clocking the shift-register.

BACKGROUND OF THE INVENTION

The present invention relates to apparatus for use in depositingarticles in a receptacle, and also to a sequence controller utilized insuch apparatus. The invention is particularly useful with respect to anapparatus enabling the deposit of envelopes in a bank in a tellerlessmanner, and is therefore described below with respect to such anapplication.

Under modern banking practices, there is a tendency to enable more andmore transactions to be made in a tellerless manner. Thus, apparatus hasbeen devised enabling the customer to withdraw a limited amount of fundsfrom a bank at any time, even when the bank is closed, by the use of anindividual machine-readable card. Apparatus has also been providedenabling the customer to make bank deposits when the bank is closed.

BRIEF SUMMARY OF THE INVENTION

The present invention provides an improved apparatus which may be usedfor depositing articles, particularly bank deposit envelopes, in areceptacle. Briefly, the apparatus comprises: a chute having an inletthrough which the articles are inserted and an outlet through which thearticles exit into the receptacle; a mechanical gate at the inlet of thechute; a mechanical gate at the outlet of the chute; an actuator foreach of the inlet and outlet gates for opening and closing same; arecording device within the chute for recording information on thearticle therein; an actuator for actuating the recording device; cycleinitiating means enabling when the inlet gate is closed for initiating adeposit cycle having a predetermined sequence of actions includingopening the inlet gate to permit insertion of the article into the chutewhile the outlet gate is closed, closing the inlet gate, actuating therecording device to record information on the article, and opening theoutlet gate to permit the article to pass into the receptacle; asequence controller controlling the actuators of the inlet gate, therecording device, and the outlet gate to enforce said predeterminedsequence of actions in the deposit cycle within specified time periods;and error detecting means terminating the deposit cycle at any stagethereof in which there occurs an action deviating from saidpredetermined sequence or not within a time period specified in thesequence.

More particularly, the sequence controller comprises: a plurality ofsensors sensing a plurality of events occurring asynchronously andproducing actuating signals in response thereto; and a sequencingcircuit including means establishing a plurality of stages according toa predetermined sequence in which the events are to occur in the depositcycle. The sequencing circuit further includes control means responsiveto the sensor actuating signal in its respective stage for actuating therespective actuator and for advancing the sequential controller to thenext stage of the deposit cycle.

The sensors, in the embodiment described below, comprise: an inlet gatesensor sensing the condition of the inlet gate; a chute sensor sensingthe condition of whether or not an article is in the chute; a printersensor sensing the condition of the printer; and an outlet gate sensorsensing the condition of the outlet gate.

The invention also provides a sequence controller, particularly usefulin the above apparatus, for controlling a plurality of devices inaccordance with a cycle having a predetermined sequence of actions andin response to a plurality of events occurring asynchronously. Brieflythe sequence controller comprises means initiating the cycle; aplurality of sensors sensing the plurality of events and producingactuating signals in response thereto; and a sequencing circuitincluding means establishing a plurality of stages according to thepredetermined sequence in which the events are to occur and controllingsaid device in response to the sensor actuating signal in its respectivestage. The sequencing circuit includes a shift register having an inputand parallel outputs one for each stage, and a logical gate for eachstage. Each logical gate produces a predetermined output signal uponreceiving an enabling signal from the shift register output of thepreceding stage in coincidence with an actuating signal from the sensorof its respective stage. The apparatus further includes means feeding asignal to the input of the shift register; clocking means responsive tosaid predetermined output signal from each of the logical gates forclocking the shift register to shift its input signal from one output tothe next in succession; and means responsive to the output signals fromthe shift register for controlling the actuators.

According to a further feature, the clocking means comprises a flip-flopreceiving the output signals from all the logical gates at one of itsinput terminals, and the inversion thereof at the other of its inputterminals; means clocking the flip-flop; and means feeding the signalsfrom one output terminal of the flip-flop to the clock input of theshift register for clocking same.

Further features and advantages of the invention will be apparent fromthe description below.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, withreference to a tellerless bank depositing apparatus illustrated in theaccompanying drawings, wherein:

FIG. 1 schematically illustrates the deposit chute in which the bankdeposits are made, including the various actuator and sensor devicesassociated with the chute;

FIG. 2 is a block diagram illustrating the overall arrangement and modeof operation of the apparatus;

FIG. 3 illustrates a particular sequential controller used in theapparatus;

FIG. 4 is a timing diagram relating to the sequential controller of FIG.3, illustrating the state changes from the normal or initial stage ofthe deposit cycle to the first stage thereof; and

FIG. 5 is a block diagram illustrating the error detector system used inthe apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENT General Arrangement

The apparatus illustrated in the drawings is one for use in making bankdeposits in a tellerless manner. Briefly, the customer depresses aDeposit key which opens the deposit gate (i.e. a mechanical gate at theinlet of the deposit chute) in the teller's fascia and also initiates adeposit cycle involving the execution of a predetermined sequence ofactions within specified time periods. The first action is the insertionof the bank deposit envelope through the slot in the fascia opened bythe inlet gate, which envelope falls down the chute until it comes upagainst the closed safe gate at the outlet end of the chute. When theenvelope reaches this position, a chute sensor is activated which causesa printer to print a transaction number on the envelope. Once this iscompleted, the safe gate at the outlet end of the chute is opened, whichallows the envelope to fall into the deposit safe. The safe gate is thenclosed, thereby completing the deposit cycle.

Sensors are provided to sense the events or conditions which must befulfilled before the apparatus can progress to the next stage of thedeposit cycle. If any of these required conditions or events does notoccur in the proper stage of the cycle, or within a predetermined timeperiod specified in the cycle, the deposit cycle is not completed andthe apparatus is reset to its normal or starting condition.

The apparatus illustrated in the drawings uses a logic arrangement,which, on receipt of a "start" control command signal (from theprocessor upon the depression of the "Deposit" key), drives theapparatus through the complete deposit cycle without further firmwareaction. On completion of the cycle, the logic is in its normal orstarting condition preparatory for a new deposit cycle.

The portion of the apparatus used in the foregoing deposit cycle isdiagrammatically illustrated in FIG. 1. It includes a chute 2 having agate 4 at the inlet thereof, and another gate 6 at the outlet endthereof. At the beginning of the deposit cycle, both of these gates areclosed. The deposit cycle is initiated by the processor (not shown) whenthe customer depresses the "Deposit" key, diagrammatically illustratedat 8, whereupon the inlet or fascia gate 4 opens to permit insertion ofthe bank deposit envelope into chute 2.

The inlet or fascia gate 4 is opened by an actuator 10, such as asolenoid, and its condition is sensed by a sensor S₁, the latter being anormally open switch which closes when the fascia gate is not fullyclosed.

After the bank deposit envelope is inserted through the open fascia gateinto chute 2, it travels downwardly by gravity to the bottom of thechute until it comes against the outlet gate 6. As the envelope arrivesto this position, it actuates a chute sensor S₂. The latter may be amicro-switch having a feeler arm 12 disposed in the chute to be engagedby the descending envelope.

At this stage, a printer 14 is actuated by an actuator diagrammaticallyillustrated by block 16. Actuator 16 cycles printer 14 so as to bringthe latter's printing head 18 into engagement with the envelope at thebottom of the chute, and then to return the printing head to its normalcondition. The printing head 18 applies a transaction number to theenvelope, and therefore is of the type which is automaticallyincremented one unit with each actuation thereof.

The actuation of the printer is sensed by a printer sensor S₃. Thelatter is another switch which is normally closed when the printer is inits normal, non-actuated condition, but is opened during the actuationof the printer.

After the printer has been actuated and returned, outlet or safe gate 6is opened by an actuator 20, such as a solenoid, to permit the envelopeto fall into the receptacle or safe 22, whereupon the gate isautomatically closed. The condition of the gate is sensed by a gatesensor S₄, in the form of a switch which is normally open but is closedwhenever the gate is not in its completely closed condition.

The apparatus illustrated in FIG. 1 further includes a jam sensor S₅ inthe form of another normally-closed switch having a feeler arm 24disposed within chute 2 above feeler arm 12 of sensor S₂. Feeler arm 24of sensor S₅ should be at a height below fascia gate 6 which is lessthan the length of the shortest envelope normally to be accommodated bythe apparatus, so that if the envelope becomes jammed within the chuteand does not reach the bottom gate 6, this will be sensed by sensorswitch S₅ being in its open condition.

In addition, the apparatus includes an indicator 24 viewable to theuser, the indicator carrying a "Make Deposit" display. This display iscontrolled by a circuit 26 so as to be illuminated when fascia gate isopened (thereby directing the user to place the bank envelope into thechute) and is extinguished as soon as the fascia gate is closed.

In the described embodiment, the deposit cycle can be initiated onlywhen both gates 4 and 6 are closed. Briefly, the deposit cycle isinitiated by depressing the Deposit key 8, whereupon the fascia gate 4is opened to permit insertion of the bank envelope into chute 2, and the"Make Deposit" display 24 is illuminated. The inserted envelope fallsdown through the chute whereupon it actuates and then deactuates jamsensor S₅, and then actuates chute sensor S₂. The latter sensor remainsin its actuated condition when the envelope reaches the safe gate 6 atthe bottom of the chute. At this point, fascia gate 4 is closed, and the"Make Deposit" display 24 is extinguished. After a predetermined time(in this case 1.25 seconds) to permit the fascia gate to close fully andthe envelope to settle at the bottom of the chute, printer 14 isactuated to apply the transaction number to the envelope, and uponreturn of the printer to its normal position as sensed by sensor S₃,safe gate 6 is opened to permit the envelope to fall into the safereceptacle 22. After a predetermined time delay (in this case 2.5seconds) the safe gate 6 is closed, and upon sensor S₄ sensing theclosed condition of the gate, the apparatus is normalized in preparationfor a new deposit cycle.

FIG. 2 illustrates in block diagram form the overall circuit arrangementof the apparatus of FIG. 1 for performing the above sequence of actionsin a deposit cycle. Briefly, the circuit includes a sequence controller,generally designated 30, which controls the fascia gate actuator 10, theprinter actuator 16, the safe gate actuator 20, and the display circuit26, to enforce the above sequence of actions and within specified timeperiods. A specific sequential controller which may be used is moreparticularly illustrated in FIG. 3, and its operation is moreparticularly described with reference to FIG. 4.

The apparatus also includes an error detecting arrangement terminatingthe deposit cycle at any stage thereof in which there occurs an actiondeviating from the predetermined sequence, or not within a time periodspecified in the sequence. An error detecting arrangement which may beused is shown in block diagram in FIG. 5.

Overall Logic Control (FIG. 2)

Referring back to the overall system illustrated in FIG. 2, it will beappreciated that the various events and conditions which control thesequence of actions in a deposit cycle, and which are sensed by thesensors S₁ -S₅, occur asynchronously. Sequential controller 30,illustrated in block form in FIG. 2, establishes a plurality of stagesaccording to the predetermined sequence in which the events are to occurin the deposit cycle, and responds to the output signals from thesensors in their respective stages for actuating the respective actuatorcontrolled by that sensor. As each actuator is actuated in itsrespective stage, the sequential controller 30 advances the system tothe next stage of the deposit cycle to await the next asynchronouslyoccurring event which actuates the actuator in that next stage.

A preferred form of sequential controller which may be used isillustrated in FIG. 3 and is described more particularly below.

For purposes of describing the overall system as illustrated in FIG. 2,it is sufficient at this point to note that the sequential controllerincludes a plurality of logic gates G₁ -G₈, one for each of the stages.All these gates are illustrated an NAND-gates having two inputs, namelya "stage" input "ST" and an "event" input "E". The stage input "ST"receives a signal from the preceding stage output of the sequentialcontroller to enable the gate for operation when it receives itsasynchronous event input "E". Thus, the gate is enabled to actuate itsrespective actuator upon receipt of the asynchronously occurring eventsignal from the respective sensor, or from another event-determiningmeans such as the run-out of a predetermined time period.

The first stage logical gate G₁ is enabled by the receipt of the stageinput "ST₀ " signal upon the completion of the previous deposit cycle,so that it will be ready to start the deposit cycle as soon as theDeposit key 8 is depressed. In this initial or starting condition, allthe actuators are deenergized, both the fascia gate 4 and the safe gate6 are closed, the "Make Deposit" display 24 is extinguished, and theprinter 14 is in its inoperative position, as illustrated in FIG. 1.

When the user desires to make a bank deposit, he depresses Deposit key8, which causes a Start Command circuit 32 to produce a signal E₁ on theevent input of gate G₁. As soon as this occurs, sequential controller 30produces an output signal via OR-gate G₉ to fascia gate actuator 10 toopen the fascia gate 4, and a further signal to circuit 26 to illuminatethe "Make Deposit" display 24.

Further, sequential controller 30 produces an output signal ST₁ which isapplied to the ST₁ input of the second stage logical gate G₂, whichthereby advances the apparatus to the second stage of the deposit cycleso that it will be ready to act as soon as it receives the commandsignal from the sensor of that stage.

Thus, during the first stage, fascia gate 4 is opened, the "MakeDeposit" display 24 is illuminated, and logical G₂ for the second stageis enabled.

As soon as fascia gate 4 partially opens, its sensor S₁ is actuated.This produces a signal E₂ to gate G₂ which, having been enabled by theenabling signal ST₁, produces an output signal via OR-gate G₉ to fasciagate actuator 10 causing fascia gate 4 to remain open, and anothersignal to circuit 26 causing the "Make Deposit" display 24 to remainilluminated. In addition, sequential controller 30 produces an outputsignal ST₂ which is applied to gate G₃ to enable the third-stageoperation in the deposit cycle.

Thus, during this second stage, initiated by sensor S₁ upon the openingof fascia gate 4, the fascia gate remains open, the "Make Deposit"display remains illuminated, and the sequential controller is advancedto enable the next stage of the deposit cycle.

The user may then insert the deposit envelope into chute 2 through theopen fascia gate 4. The envelope drops through the chute, firstactuating feeler 24 of jam sensor S₅ and then feeler 12 of chute sensorS₂, until it reaches the bottom of the chute where it is blocked fromexiting into the safe 22 by the closed safe gate 6. Assuming theenvelope properly reaches the bottom of the chute, jam sensor S₅ is inits deactuated condition, whereas chute sensor S₂ is in its actuatedcondition.

The third stage of the deposit cycle is initiated by chute sensor S₂.Its detection of the arrival of the deposit envelope to the bottom ofthe chute assures that the envelope has cleared the fascia gate. As soonas sensor S₂ is actuated, it produces signal E₃ to gate G₃, whereby thesequential controller 30 produces an output signal to actuator 10 toclose fascia gate 4, and also to circuit 26 to extinguish the "MakeDeposit" dispaly 24. At the same time, the sequential controllerproduces an output ST₃ which is applied to the fourth stage gate G₄ toenable that gate to act upon the occurrence of the relevant event orcondition of that respective stage.

The fourth stage gate G₄ acts as soon as two conditions have occurred,namely, (1) fascia gate 4 has moved into its completely closed position,and (2) a specified time period (in this case 1.25 seconds) has run out,to allow the fascia gate 4 to completely close and the deposit envelopeto settle in the bottom of the chute.

The latter condition is implemented by a timer circuit 34 applying asignal to one input of an AND-gate G₁₀, and the former condition isdetermined by the absence of a signal from sensor S₁, also applied toAND-gate G₁₀. The output of AND-gate G₁₀ is signal E₄ applied toNAND-gate G₄ which, in coincidence with the enabling signal ST₃ from thepreceding stage, initiates the fourth stage of the deposit cycle.

In the fourth stage the sequential controller 30 produces an outputwhich is applied via NOR-gate G₁₁ to printer actuator 16 to actuateprinter 14. The printer is thus actuated to cause its printing head 18to apply a transaction number to the deposit envelope at the bottom ofthe chute, the printer then returning to its normal position. Asindicated earlier, the printer is one that is automatically incrementedwith each operation so that sequential transaction numbers are appliedto the deposit bank envelopes.

The fourth stage of sequential controller 30 also produces an outputsignal ST₄ which is applied to the fifth stage G₅ to enable the fifthstage operation in the deposit cycle.

The fifth stage is initiated by signal E₅ from printer sensor S₃ whilethe printer is in operation, the sequential controller producing anoutput signal ST₅ applied via OR-gate G₁₁ to printer actuator 16 tomaintain the actuating of the printing.

The sixth stage is enabled by signal ST₅ and is initiated as soon as theprinter 14 has completed its cycle and has returned to its normalcondition. When this occurs, the signal from printer sensor S₃ ceases,the lack of a signal from sensor S₃ being input signal E₆ to logic gateG₆ to initiate the sixth stage of the deposit cycle. During this sixthstage, safe gate actuator 20 is actuated to open safe gate 6, and inaddition an output signal ST₆ is fed to logic gate G₇ of the seventhstage in the deposit cycle.

The seventh stage is initiated upon the elapse of a specified timeperiod (in this case 2.5 seconds) to permit the envelope to drop intothe safe 22 after the safe gate has been opened. After the elapse ofthis time period, as implemented by timer 36 producing signal E₇ to gateG₇, the sequential controller 30 produces an output signal ST₇ appliedto safe gate actuator 20 to close gate 6, and also to enable the eighthstage of the deposit cycle.

The eighth stage is initiated when safe gate sensor S₄ senses thecondition that the safe gate 6 has been closed, thereby producing asignal E₈ applied to logic gate G₈. When this occurs, sequentialcontroller 30 produces an output signal ST₈ which is applied to acircuit 38 for resetting the sequential controller and for producing theenabling signal ST₀ applied to the first stage electonic gate G₁.

The deposit cycle is thus completed, and the first-stage gate G₁ isenabled by signal ST₀ in preparation for the execution of anotherdeposit cycle. The next cycle is initiated by another depression of theDeposit key 8.

Sequential Controller (FIGS. 3 and 4)

An improved sequential controller that may be used is illustrated inFIG. 3, and its operation will be better understood by the timingdiagram of FIG. 4.

The sequential controller 30 illustrated in FIG. 3 includes as MSI 8-bitshift register SR having serial inputs and parallel outputs, there beingone output stage for each cycle stage of the sequential controller.Thus, the outputs of the shift-register are labelled ST₁ -ST₈, andcorrespond to the identically numbered output terminals ST₁ -ST₈ of thesequential controller 30 in FIG. 2.

The shifter-register SR is automatically reset at the completion of eachdeposit cycle. For this purpose, the signal appearing on the last outputterminal ST₈ of the shift-register is applied to resetting circuit 38consisting of a JK flip-flop FF₁, the output of which circuit is fed tothe reset terminal of the shift-register.

The shift-register may also be reset before the completion of thedeposit cycle, e.g. by an error condition. The latter reset signal isderived from circuit 39 (e.g. the error circuit described below) and islikewise fed, via NOR-gate 40 and flip-flop FF₁, to the reset terminalof the shift-register.

The above signals used to reset the shift-register SR, and thereby thesequential controller 30, are also applied to the "set" terminal of aflip-flop FF₂. The latter, in its set state, produces the ST₀ signalapplied to the first-stage logical gate G₁ for enabling that gate, andthereby for placing the apparatus in condition for executing a depositcycle as soon as the cycle is initiated by depressing the Deposit key 8,as discussed above.

When flip-flop FF₂ is set, the output signal ST₀ is also applied to theserial input of shift-register SR.

Thus, in the starting or normal condition of the circuit, the signal oninput terminal ST₀ of the first-stage logical gate G₁ is "true" therebyenabling that gate, whereas the signals on the input terminals ST₁ -ST₇of logical gates G₁ -G₇ are "false" thereby disabling these gates. Also,flip-flop FF₂ is in its "set" condition, and all the outputs ofshift-register SR are in their "reset" condition. In addition, thesignals on the "events" input terminals E₁ -E₈ of all the logical gatesG₁ -G₈ are "false".

The circuit remains in this state until event E₁ occurs, namely thedepression of Deposit key 8 to initiate a deposit cycle. When thisoccurs, an output signal is produced from logical gate G₁ which is fedto a clocking circuit 41 (described below) for the shift-register, toshift the input signal to its output line ST₁, and thereby to produceoutput signal ST₁. The latter initiates the first-stage operation of thedeposit cycle as described above, and also enables the second-stagelogical gate G₂.

The circuit now is ready for the second-stage event, namely the sensingby sensor S₁ of the open condition of the fascia gate 4.

The clocking circuit 41, receiving the output signal from logical gateG₁ in order to clock the shift-register SR, includes a further flip-flopFF₃ of the JK-type. The output signals from all the logical gates G₁ -G₈are fed via inverter 42 to the K-terminal of the flip-flop, and thenthrough a second inverter 44 to the J-terminal of the flip-flop. TheQ-output terminal of the flip-flop is connected to the clock terminal ofshift-register SR, whereas the complementary Q-output terminal isconnected via inverter 46 to the K-input terminal of the flip-flop.

FIG. 4 illustrates the timing diagram of the state change from the ST₀state of the shift-register to the next state ST₁. Signal A representsthe clock applied to flip-flop FF₃ ; signal B represents the ST₀ signalwhich as noted above is "true" in the normal or starting condition ofthe apparatus, i.e. in the reset state of shift-register SR; signal Crepresents the ST₁ signal which is "false" in the normal condition ofthe apparatus; signal D represents the E₁ signal applied to thefirst-stage logical gate G₁ to initiate the first stage of the depositcycle; signal E represents the signal appearing at the K-input terminalof flip-flop FF₃ ; and signal F represents the signal appearing at theQ-output terminal of flip-flop FF₃.

It will be seen from the timing diagram of FIG. 4 that the occurrence ofevent E₁ (namely the sensing of the open condition of fascia gate 4 bysensor S₁) causes the E₁ signal D to go "true", and (a short timethereafter owing to the delay of inverter 42) causes the signal Eapplied to the K-input terminal of flip-flop FF₃ also to go "true". TheQ-output signal F of flip-flop FF₃, which originally was "true", doesnot change until the falling edge of the next clock pulse A, at whichtime it, as well as signal E, both go "false". At the falling edge ofthe next clock pulse A, signal F goes "true", and its rising edge F'clocks the shift-register ST to shift the signal to its output terminalST₁, whereupon signal C (ST₁) goes "true" and signal B (ST_(o)) goes"false".

At the time the shift-register SR is clocked, a spike E' may appear withrespect to signal E, but this spike would be ineffective since the clocksignal A is "false" at that time and therefore flip-flop FF₃ isinhibited.

As soon as the first stage has been initiated by signal E₁, thefirst-stage gate G₁ is disabled by the ST₁ pulse applied from outputline ST₁ of the shift-register to flip-flop FF₂, which resets theflip-flop and thereby makes the ST_(o) output "false". Thus, as soon asthe cycle has been initiated and the second-stage logical gate G₂enabled, the first-stage logical gate G₁ is disabled so that anysubsequent depression of the Deposit key 8 will be ineffective.

The second stage of the deposit cycle is initiated as soon as the fasciagate 4 partially opens, this being sensed by sensor S₁ which producesthe E₂ signal applied to the second-stage logical gate G₂. The lattergate, previously enabled by the ST₁ signal from the shift-register,produces an output signal which is applied to the clocking circuit 41for the shift-register to shift the input signal therein to the nextoutput line, namely output ST₂. This initiates the second stage of thedeposit cycle described above and also enables the third-stage logicalgate G₃.

The outputs from the other logical gates G₃ -G₈ are applied in the samemanner to the clocking circuit 41 for clocking the shift-register toshift its input signal from one output to the next in succession,thereby initiating the operation of that stage in the deposit cycle andenabling the logical gate for the next succeeding stage.

Error Detecting Arrangement

FIG. 5 illustrates the error detecting arrangement which terminates thedeposit cycle at any stage thereof in which there occurs an actiondeviating from the predetermined sequence of the deposit cycle, or notwithin a time period specified in the sequence.

Thus, as shown in FIG. 5, the apparatus includes a timer T having aninput terminal Ts for starting the timing operation, a second inputterminal Tr for resetting the timer which is done at the start of eachnew stage, and a further input terminal Tc for clocking the timer. Thetimer includes a plurality of output terminals according to thedifferent time periods that may be utilized in the deposit cycle. Thus,one output terminal To₁ receives an output signal after the elapse of1.25 seconds, a second output terminal To₂ receives a signal after theelapse of 2.5 seconds, a third output terminal To₃ receives a signalafter the elapse of 5 seconds, and so forth, there being as manyterminals as timer periods desired.

The error detecting arrangement illustrated in FIG. 5 sets up a numberof error conditions any one of which will actuate an error flip-flopincluding two cross-connected NAND-gates G₁₁, G₁₂. For each of the errorconditions, there is provided a logical gate G₁₃ -G₁₉ the outputs ofwhich are fed via an OR-gate G₂₀ to the error flip-flop gates G₁₁, G₁₂.When the error flip-flop is actuated by one of the foregoing signals, itproduces an error signal via circuit 39 which may be used to control anindicator or the like. This error signal is also applied to the Resercircuit (FIG. 3) of the shift-register to reset it and thereby toterminate the deposit cycle before it is completed. As describedearlier, resetting the shift-register sets flip-flop FF₂, which producesoutput signal ST_(o) enabling the first-stage logical gate G₁ for thestart of a new deposit cycle.

The first error logical gate G₁₃ detects the condition that any one ofthe sensors S₂ -S₅ may be actuated while the circuit is in the firststage of the deposit cycle. It will be recalled, that the first stage isinitiated by the depression of the "Deposit" key 8 and is terminated assoon as the fascia gate 4 is fully opened. If during this time the chutesensor S₂, the printer sensor S₃, the gates sensor S₄, or the jam sensorS₅, is in its actuated condition, a signal will be generated via OR-gate21 and NAND-gate G₁₃ and fed via OR-gate 20 to the error flip-flop gatesG₁₁, G₁₂ to error circuit 50.

A second error condition detected by the circuit of FIG. 5 is the elapseof a specified time period, in this case 1.25 seconds, while the circuitis still in the first stage of the deposit cycle. Thus, if the fasciagate 4 has been commanded to open by signal E₁ but does not reach itsfully open condition, (as sensed by sensor S₁ terminating the firststage) after the elapse of 1.25 seconds (which may arise because ofjamming of the fascia gate), an error signal is produced by logical gateG₁₄ via Or-gate G₂₀.

Logical gate G₁₅ in the error circuit of FIG. 5 detects a further errorcondition, namely the condition that chute sensor S₂ has not yet beenactuated after 40 seconds have elapsed since the start of the secondstage of the deposit cycle. It will be recalled from above that thissecond stage is initiated by the opening of the fascia gate 4 (detectedby sensor S₁) to permit the insertion of the bank deposit envelope. Ifthis has not been inserted within 40 seconds from the start of thatstage, as detected by chute sensor S₂, and if the jam sensor S₅indicates (true) that an envelope has jammed, a signal is produced tothe error flip-flop via gates G₁₅ and G₂₀.

Logical gate G₁₆ detects the error condition that five seconds haveelapsed since the start of the fourth stage of the deposit cycle and thecycle has not yet progressed to the fifth stage. It will be recalledthat the fourth stage is initiated 1.25 seconds after the fascia gatehas closed (S₁), and is terminated by the start of movement of theprinter 14 (S₃). Thus, if the printer does not start to move within 5seconds of the time it was commanded to do so (by gate G₄) a signal isproduced via gates G₁₇ and G₂₀ to the error flip-flop gates G₁₁, G₁₂.

Logical gate G₁₈ detects the error condition wherein the apparatus is inthe sixth stage of the deposit cycle, 1.25 seconds have elapsed sincethe start of the sixth stage, and safe gate 6 is still in its normalclosed condition. It will be recalled that the sixth stage is initiatedby signal E₆ which is produced after the printer has returned to itsnormal condition (S₃). At this time the safe gate 6 is commanded bylogical gate G₆, and if it does not start to do so within the 1.25seconds specified, a signal is produced via gates G₁₈ and G₂₀ to errorflip-flop gates G₁₁, G₁₂.

Finally, logical gate G₁₉ detects the error condition wherein theapparatus is in the seventh stage of the deposit cycle, and either aperiod of 2.5 seconds has elapsed, or the chute sensor S₂ is stillactuated, before the seventh stage is terminated and the system is resetto its initial condition. The seventh stage is initiated by signal E₇,which starts the safe gate to open, thereby permitting the envelope tofall into the safe 22. If the envelope does not fall into the safewithin the specified timer period of 5 seconds, as detected by chutesensor S₂, an output signal is produced by gates G₂₁, G₁₉ and G₂₀ toerror flip-flop gates G₁₁, G₁₂.

As pointed out earlier, an error signal from the error flip-flop gatesG₁₁, G₁₂ caused by any of the foregoing conditions, will result in theimmediate termination of the deposit cycle, and resetting the system toits starting condition.

The foregoing are merely some examples of error conditions. Many otherscould be included.

Summary of Operations

In the normal or starting condition of the apparatus, both the fasciagate 4 and the safe gate 6 at the inlet and outlet ends, respectively,of the chute 2 are closed, and printer 14 is in its normal, non-actuatedcondition, all as illustrated in FIG. 1. In addition, the "Make Deposit"display 24 is non-illuminated. In the shift-register circuit illustratedin FIG. 3, the stage-enabling input signal ST_(o) to the first-stagelogical gate G₁ is "true", whereas the other stage-enabling signals ST₁-ST₇ are "false". The event signals E₁ -E₈ are all "false". Further,flip-flop FF₂ is in its set condition, and shift-register SR is in itsreset condition. The apparatus is now ready for execution of the depositcycle.

To initiate a deposit cycle, the user depresses Deposit key 8, whichproduces a "true" start command E₁ fed to the first-stage logical gateG₁. Other actions by the user, in addition to the depression of theDeposit key 8, such as the insertion of a machine-readable personal cardissued to that particular user, may be permitted or required, but suchother actions are not involved in the present invention and aretherefore not described herein.

As soon as the user depresses the Deposit key 8, a signal is produced bylogical gate G₁ to fascia gate actuator 10 opening the fascia gate 4,and to circuit 26 illuminating the "Make Deposit" display 24.

In addition, a "true" enabling signal ST₁ is applied to the second stagelogical gate G₂.

The foregoing is accomplished in the sequential controller 30illustrated in FIG. 3 by applying the output pulse from gate G₁ to theclocking circuit 41 including flip-flop FF₃, the latter producing aclocking pulse to shift-register SR which shifts the signal to theoutput line ST₁ so that the signal on the latter line now becomes"true". This signal also resets flip-flop FF₂ so that its output ST_(o)now becomes "false", thereby disabling the Deposit key 8 from thereafterinitiating another deposit cycle, until the present cycle is completedor terminated.

Thus, during the first stage of the deposit cycle, fascia gate 4 isactuated to open and the "Make Deposit"display 24 is illuminated.

As soon as the fascia gate has been completely opened, it actuatessensor S₁ which terminates the first stage of the deposit cycle andinitiates the second stage. This is accomplished by logical gate G₂which produces a clock pulse from flip-flop FF₃ of clocking circuit 41,the latter being applied to shift-register SR to shift its signal tooutput terminal ST₂. During this second stage, fascia gate 4 remainsactuated and the "Make Deposit" display remains illuminated, and inaddition, the output pulses on line ST₂ is applied to the third stagegate G₃ to enable that stage.

As soon as the fascia gate 4 opens during the first and second stages ofthe deposit cycle, the user may place the deposit envelope within chute2, whereupon the envelope drops by gravity through the chute andactuates feeler arm 24 of jam sensor S₅ and then feeler arm 12 of chutesensor S₂. Since safe gate 6 is in its closed condition, the gate willprevent the envelope from falling into the safe 22, and therefore sensorS₂ will remain in its actuated condition.

As soon as chute sensor S₂ is actuated, a "true" signal E₃ is applied tological gate G₃ which is effective to step shift-register SR oneposition so that its output ST₃ becomes "true". This signal is appliedto fascia gate actuator 10 to close that gate and also to circuit 26 toextinguish the "Make Deposit" display, and in addition to logical gateG₄ to enable the fourth stage of the deposit cycle.

The fourth stage is not initiated until the lapse of 1.25 seconds, asdetermined by timer 34 in FIG. 2, to enable the fascia gate tocompletely close and the envelope to settle in the bottom of the chute.As soon as this period of time has elapsed, and assuming that the fasciagate has fully closed (as determined by the "false" signal S₁ fromfascia gate sensor S₁ applied via G₉ to gate G₄), the latter logicalgate produces an output signal which steps shift-register one positionso that its output line ST₅ now becomes "true".

The latter signal is applied to printer actuator 16 to actuate printer14, whereupon the printer applies a transaction number to the envelopewithin the chute, and then returns to its normal position. The ST₄signal also enables the fifth-stage gate G₅ which stage is initiated bysensor S₃ as soon as the printer is actuated.

When the printer returns to its normal condition as sensed by the"false" signal S₃ from printer sensor S₃, the sixth stage is initiatedby logical gate G₆ to shift the shift-register SR output to make itsoutput line ST₆ "true". The latter signal is applied to the safe gateactuator 20 to open the gate, and is also applied to the seventh-stagelogical gate G₇ to enable that gate.

The seventh stage is initiated 2.5 seconds thereafter to enable the safegate to fully open. After the elapse of this time period, as determinedby timer block 36, the seventh-stage logical gate G₇ stepsshift-register SR so that its output line ST₇ now becomes "true". Thelatter signal is applied to safe gate actuator 20 to close the safegate, and also to the eighth-stage logical gate G₈ to enable that gatefor the eighth stage operation.

The eighth stage is initiated by safe gate sensor S₄ sensing the returnof safe gate 20 to its normal closed position, whereupon logical gate G₈shift-register SR to shift the signal to its output line ST₈. Thissignal is applied to the reset circuit 38 which resets shift-register SRand also places flip-flop FF₂ in its set condition, whereby its outputterminal ST_(o) is "true".

The deposit cycle is thus completed, and the circuit is enabled for theinitiation of a new deposit cycle by the next user depressing Depositkey 8.

In the event there occurs, during any stage in the deposit cycle, anaction or condition deviating from the predetermined sequence, or notwithin a time period specified in the sequence, the error flip-flopcomprising the cross-connected error gates G₁₁, G₁₂ illustrated in FIG.5 is set to produce an error signal output from error circuit 39. Thiserror signal terminates the deposit cycle by actuating the resettingcircuit 38 (FIG. 3) to the shift-register and causing flip-flop FF₂ togo to its set condition producing a "true" output ST_(o). The variousconditions which produce the error operation are implemented by logicalgates G₁₃ -G₁₉ of FIG. 5.

While the invention has been described particularly with reference to anapparatus enabling the deposit of bank envelopes in a tellerless manner,it will be appreciated that some or all of the features of the inventioncould advantageously be used in other applications.

Many variations, modifications, and other applications of the inventionwill therefore be apparent.

What is claimed is:
 1. Apparatus for use in depositing articles, such asbank deposit envelopes, in a receptacle, comprising:a chute having aninlet through which the articles are inserted and an outlet throughwhich the articles exit into the receptacle; a mechanical gate at theinlet of the chute; a mechanical gate at the outlet of the chute; anactuator for each of the inlet and outlet gates for opening and closingsame; a recording device within the chute for recording information onthe article therein; an actuator for actuating the recording device;cycle initiating means enabled when the inlet gate is closed forinitiating a deposit cycle having a predetermined sequence of actionsincluding opening the inlet gate to permit insertion of the article intothe chute while the outlet gate is closed, closing the inlet gate,actuating the recording device to record information on the article, andopening the outlet gate to permit the article to pass into thereceptacle; a sequence controller controlling the actuators of the inletgate, the recording device, and the outlet gate to enforce saidpredetermined sequence of actions in the deposit cycle within specifiedtime periods; and error detecting means terminating the deposit cycle atany stage thereof in which there occurs an action deviating from saidpredetermined sequence or not within a time period specified in thesequence.
 2. Apparatus according to claim 1, wherein said sequencecontroller comprises:means including a plurality of sensors sensing aplurality of events occurring asynchronously and producing actuatingsignals in response thereto; and a sequencing circuit including meansestablishing a plurality of stages according to a predetermined sequencein which the events are to occur in the deposit cycle; said sequencingcircuit further including control means responsive to the sensoractuating signal in its respective stage for actuating the respectiveactuator and for advancing the sequential controller to the next stageof the deposit cycle.
 3. Apparatus according to claim 2, wherein saidmeans sensing the plurality of asynchronously occurring eventscomprises:an inlet gate sensor sensing the condition of the inlet gate;a chute sensor sensing the condition of whether or not an article is inthe chute; a printer sensor sensing the condition of the printer; and anoutlet gate sensor sensing the condition of the outlet gate. 4.Apparatus according to claim 2, wherein said sequencing circuitincludes:a shift register having an input and parallel outputs one foreach stage; a logical gate for each stage; each logical gate producing apredetermined output signal upon receiving an enabling signal from theshift-register output of the preceding stage in coincidence with anactuating signal from the sensor of its respective stage; means feedinga signal to the input of the shift-register; clocking means responsiveto said predetermined output signal from each of the logical gates forclocking the shift-register to shift its input signal from one output tothe next in succession; and means responsive to the output signals fromthe shift-register for controlling the actuators.
 5. Apparatus accordingto claim 4, wherein:said clocking means comprises a flip-flop receivingthe output signals from all the logical gates at one of its inputterminals, and the inversion thereof at the other of its inputterminals; means clocking the flip-flop; and means feeding the signalsfrom one output terminal of the flip-flop to the clock input of theshift-register for clocking same.
 6. Apparatus according to claim 4,further including means connected to the last stage of theshift-register for resetting same.
 7. Apparatus according to claim 1,wherein the cycle means is enabled when both the inlet and outletmechanical gates are closed, the outlet mechanical gate being closed atthe end of the deposit cycle.
 8. Apparatus according to claim 1, whereinsaid error detecting means further includes a jam sensor sensing the jamof an article in the chute and terminating the deposit cycle in responsethereto.
 9. Apparatus for use in depositing articles, such as bankdeposit envelopes, in a receptacle, comprising:a chute having an inletfor receiving articles and an outlet for discharging said receivedarticles into said receptacle; actuatable recording means within saidchute for recording information on articles received therein; depositcycle initiating means enabled when an article is received by said inletfor initiating a deposit cycle comprising a predetermined sequence oftimed actions; a sequence controller for controlling the performance ofsaid predetermined sequence of timed actions in the deposit cycle withinspecified time intervals; error detecting means for terminating thedeposit cycle at any stage thereof when one of said predeterminedsequence of timed actions is not performed within the time intervalspecified in the sequence, said error detecting means having a timerpulse generating means for associating a time interval for performingeach action in said predetermined sequence; and means within said errordetecting means for generating an error signal when an action in saidpredetermined sequence has not been performed within its associated timeinterval.
 10. The apparatus of claim 9 wherein said sequence controllercomprises:a plurality of sensors for sensing a plurality of eventsoccurring asynchronously and for producing actuating signals in responsethereto; and a sequencing circuit including means establishing aplurality of stages according to a predetermined sequence in which theevents are to occur in the deposit cycle, said sequencing circuitfurther including control means responsive to the sensor actuatingsignal in its respective stage for advancing the sequential controllerto the next stage of the deposit cycle.
 11. The apparatus of claim 10wherein said means for generating an error signal comprises a pluralityof logic gates wherein each one of said plurality of logic gates isassociated with a respective one of said plurality of said sensors, eachsaid logic gate receiving the actuating signal from its associatedsensor and a time interval terminating pulse from said timer pulsegenerating means whereby said logic gates combine said received signalsto determine if an action has been performed within its associated timeinterval.